The present invention relates to a data processing circuit and more particularly relates to the data processing circuit of the type which is favorably utilized for a memory that data which has been written into the memory is protected with an error correction code and also favorably utilized for error correction processing to be performed on the data which is read out of the memory.
In order to improve the reliability of the memory, there is adopted the memory of the type configured to store main body data to be stored by adding an error correction code (ECC) to the main body data so as to perform error detection and error correction processing on the read-out data. In such a memory as mentioned above, a single error correction-double error detection (SECDED) code with which a single-bit error is corrected and a double-bit error is detected (the double-bit error is uncorrectable) is frequently used.
In Japanese Unexamined Patent Application Publication No. Hei 5(1993)-165736, a circuit system which corrects the double-bit error by a simple circuit by using the SECDED code is disclosed.
In Japanese Unexamined Patent Application Publication No. Hei 10(1998)-97471, a method of correcting errors in data stored in the memory in block transfer of the data is disclosed. The ECC code is added to whole data block, the data block is divided into a plurality of data strings and a parity bit is added to each data string.
As a result of examinations that the inventors and others of the present invention performed on the system and the method respectively disclosed in Japanese Unexamined Patent Application Publication Nos. Hei 5(1993)-165736 and Hei 10(1998)-97471, it was found that there still remain new subject matters as follows.
In the memory to which an access is made from a processor such as a CPU (Central Processing Unit) and so forth, an instruction code length (for example, a 32-bit instruction, a 64-bit instruction and so forth), a data length or the like is set as an access unit that the access is made to the memory. However, a circuit configuration of the memory itself has such a tendency that the data length per word is increased in order of 128 bits, 256 bits and so on more steeply than the access unit. Therefore, when reading data, part corresponding to an address reading of which has been requested is physically cut out of the data to be read out word by word and is output. At that time, the ECC code is added to one-word data. That is, part of the bit length to be read out word by word is main body data and other part is ECC additional bits generated from the main body data. An error correction processing circuit generates syndromes from the whole read-out data (the main body data and the ECC additional bits), decides presence/absence of an error, a single-bit error or a double-bit error as an error type, outputs a result of decision and, in the presence of the single-bit error, corrects the error in the main body data and outputs the main body data.
Since inputting of all of the main body data and the ECC additional bits is necessary for generation of the syndromes and decision of the error type, in general, a time taken for decision of the error type is increased in proportion to a logarithm of the data length. For example, when nine ECC additional bits are added to 128-bit data, a delay taken for decision of the error type is estimated to be eight two-input exclusive OR gates and five two-input OR gates. When ten ECC additional bits are added to 256-bit data, the delay is estimated to be nine two-input exclusive OR gates and five two-input OR gates. The delay depends on the number of such gates which are serially arranged and also depends on a wiring load to be exerted with an increase in scale of the gates which are arranged in a parallel direction. As mentioned above, the delay taken for generation of the syndromes and decision of the error type largely depends on the data length.
On the other hand, it was found that there is a tendency that speeding-up of the processor is demanded and the possibility that the delay taken for generation of the syndromes and decision of the error type may become a dominant cause for impeding an increase in access speed of the memory and impeding speeding-up of the processor is high.